library ieee use ieee std_logic_1164 all entity div_dp1 is generic int

library ieee;
use ieee.std_logic_1164.all;

entity div_dp1 is
generic(n:integer:=4);
port(a,b : in std_logic_vector((n-1) downto 0);
	    res,rev: out std_logic_vector((n-1) downto 0);
	  clk: in std_logic;
	r_mode0, r_mode1: in std_logic;
      q_mode0, q_mode1: in std_logic;
    			 ex_out: out std_logic;
b_enable, alu_enable, alu_type, bit_enable: in std_logic);
end div_dp1;

architecture struct of div_dp1 is
--------------- компоненты ------------------------
component dff_1
	port(d,clk,e: in std_logic;
			   q: out std_logic);
end component;

component reg1
generic (size: integer);
	port (enbl, clk : in std_logic;
					dl : in std_logic_vector((size-1) downto 0);
					q : out std_logic_vector((size-1) downto 0));
end component;

component shreg1
GENERIC(size: positive:=4);
	PORT(s0,s1,clk,din1,din2: in std_logic;
		 dl: in std_logic_vector((size-1) downto 0);
		 q: out std_logic_vector((size-1) downto 0);
		 dout1,dout2: out std_logic);
end component;

component adder_4
generic(n: integer);
	port(a,b : in std_logic_vector((n-1) downto 0);
  cin, alu_enable: in std_logic;
		  sum: out std_logic_vector((n-1) downto 0);
		 cout: out std_logic);
end component;

---------- внутренние сигналы ----------
signal r_out, alu_out, b_out : std_logic_vector((n-1) downto 0);
signal q_out1, q_out2, c_out, scan_out1,scan_out2, carry_in, gnd, ex : std_logic;
-------------- работа --------------
begin
	gnd <= '0';
	carry_in <= not ex;
	------------ работа регистра R - компонента shreg_1
	R1: shreg1 generic map(n) port map (r_mode0, r_mode1, clk, q_out1, gnd, alu_out((n-1) downto 0),
r_out((n-1) downto 0), scan_out1, scan_out2);
	------------ работа триггера - компонента dff_1
	C1: dff_1 port map(carry_in, clk, bit_enable, c_out);
	------------ работа регистра B - компонента reg_1
	M1: reg1 generic map(n) port map(b_enable, clk, b((n-1) downto 0), b_out((n-1) downto 0));
	------------ работа регистра Q - компонента shreg_1
	Q1: shreg1 generic map(n) port map(q_mode0, q_mode1, clk, c_out, scan_out2, a((n-1) downto 0),res((n-1) downto 0),q_out1,q_out2);
	--------- работа алу - компонент адер --------------------------
	ALU1: adder_4 generic map(n) port map(r_out((n-1) downto 0), b_out((n-1) downto 0), alu_type, alu_enable, 
alu_out((n-1) downto 0),ex);

	rev <= r_out;
	ex_out <= ex;
end struct;

configuration con of div_dp1 is
	for struct
		for all: dff_1 use entity work.dff_1(beh);
		end for;
		for all: reg1 use entity work.reg1(struct);
		end for;
		for all: shreg1 use entity work.shreg1(struct);
		end for;
		for all: adder_4 use entity work.adder_4(beh);
		end for;
	end for;
end con;