library IEEE;
use IEEE.std_logic_1164.all;


entity jk_counter is
    generic( size : integer := 3 );
    port( d, clk, reset : in  std_logic;
              qOut : out std_logic_vector( size downto 0 ) 
        );
end jk_counter;

architecture mainArch of jk_counter is 
component jk_tr
    port( j, k, clk, reset : in  std_logic;
          q : out std_logic
        );
end component;

signal currentState : std_logic_vector( size downto 0 );
signal negative : std_logic_vector( size downto 0 );

begin

first_jk:   jk_tr port map ( d, d, clk, reset, currentState( 0 ) ); 

negative( 0 ) <= not currentState( 0 );

mainLoop:
		for i in 1 to size generate
others_jk:  jk_tr port map( d, d, 
                            negative( i - 1 ), reset, currentState( i ) );
   			negative( i ) <= not currentState( i );
        end generate;
    
    qOut <= currentState;
end mainArch;