library IEEE use IEEE std_logic_1164 all entity jk_tr is port clk rese

library IEEE;
use IEEE.std_logic_1164.all;


entity jk_tr is
    port( j, k, clk, reset : in  std_logic;
          q : out std_logic
        );
end jk_tr;


architecture mainArch of jk_tr is 
signal inQ : std_logic;
begin
    process( clk ) begin
        if(  reset = '0' ) then
            inQ <= '0';
        elsif( clk'event and clk = '1' ) then
            if( j = '0' and k = '1' ) then
                inQ <= '0';
            elsif( j = '1' and k = '0' ) then
                inQ <= '1';
            elsif( j = '1' and k = '1' ) then
                inQ <= not inQ;    
            end if;            
        end if;
    end process;
    q <= inQ;
end mainArch;