LIBRARY ieee use ieee std_logic_1164 all ENTITY div_1 IS generic integ

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LIBRARY ieee;
use ieee.std_logic_1164.all;
ENTITY div_1 IS
generic(n: integer:=4);
PORT(reset: IN std_logic;
start: IN std_logic;
aa,bb: in std_logic_vector((n-1)downto 0);
rs,rv: out std_logic_vector((n-1)downto 0);
clk: in std_logic);
END div_1;
architecture beh of div_1 is
signal iex: std_logic;
signal ialu_enable: std_logic;
signal ialu_type: std_logic;
signal ir_mode0: std_logic;
signal ir_mode1: std_logic;
signal ibit_enable: std_logic;
signal ib_enable: std_logic;
signal iq_mode0: std_logic;
signal iq_mode1: std_logic;
component div_dp1
generic(n:integer:=4);
port(a,b : in std_logic_vector((n-1) downto 0);
res,rev: out std_logic_vector((n-1) downto 0);
clk: in std_logic;
r_mode0, r_mode1: in std_logic;
q_mode0, q_mode1: in std_logic;
ex_out: out std_logic;
b_enable, alu_enable, alu_type, bit_enable: in std_logic);
end component;
component div_cu1
PORT(reset: IN std_logic;
start: IN std_logic;
c_ex: IN std_logic;
clk: IN std_logic;
r_mode0: OUT std_logic;
r_mode1: OUT std_logic;
alu_enable: OUT std_logic;
alu_type: OUT std_logic ;
bit_enable: OUT std_logic;
b_enable: OUT std_logic;
q_mode0: OUT std_logic;
q_mode1: OUT std_logic);
end component;
begin
d0: div_cu1 port map(reset,start,iex,clk,ir_mode0, ir_mode1,ialu_enable,
ialu_type,ibit_enable,ib_enable,iq_mode0,iq_mode1);
d1: div_dp1 generic map(n) port map(aa,bb,rs,rv,clk,
ir_mode0,ir_mode1,iq_mode0,iq_mode1,iex,ib_enable,ialu_enable, ialu_type,ibit_enable);
end beh;