OTG Ready OTG Ready-1 Full Speed Phy Reset Fail Work around solution E

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*** OTG Ready ****************************
*** OTG Ready-1 ****************************
*** Full Speed Phy Reset Fail Work around solution => Enable 0x80 Bit28
*** OTG Ready-2 ****************************
1. USB0
2. USB1
======= Select the item =>
select1 32
1. USB0 mini-A Host Mode
2. USB0 mini-B Peripheral Mode
======= Select the item =>
register ISR in hal function
************************** Peripheral Mode ***********************
-- Normal--
1.Peripheral Mode (Path Test)
2.Peripheral Mode (VBUS off=>Still in the peripheral mode )
3.Reflash
7.Dump Memory
9.FPGA Half Speed (HCLK < 30 ==> Enable)((HCLK >= 30 ==> Disable)
******************************************************************
>>> (Device-B / Peripheral Mode) Input Command :
Item 31
@@@ Device-B Enter Peripheral Mode...
>>> Enter Peripheral Mode...
malloc u8VirtOTGMemory
malloc u32VirtOTGMemory
ControlOTGCmd.Type 0 *standard command*
bGet_OTGdescriptor
get device descriptor
***eOTGCxFinishAction 1
ControlOTGCmd.Type 0 *standard command*
bSet_OTGaddress
***eOTGCxFinishAction 1
ControlOTGCmd.Type 0 *standard command*
bGet_OTGdescriptor
get device descriptor
***eOTGCxFinishAction 1
ControlOTGCmd.Type 0 *standard command*
bGet_OTGdescriptor
get config descriptor
***eOTGCxFinishAction 1