entity curcuit1 is end curcuit1 architecture struct_1 of curcuit1 is c

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
entity curcuit1 is
end curcuit1;
architecture struct_1 of curcuit1 is
component my
port (
x1, x2, x3, x4 : in bit;
y1, y2, y3, y4, y5 : out bit
);
end component;
component no2
port (
a, b : in bit;
y : out bit
);
end component;
component no4
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component o2
port (
a, b : in bit;
y : out bit
);
end component;
component no3
port (
a, b, c : in bit;
y : out bit
);
end component;
component nao3
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component noao2
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component na3o2
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component n
port (
a : in bit;
y : out bit
);
end component;
component na4
port (
a, b, c, d : in bit;
y : out bit
);
end component;
signal x1, x2, x3, x4: BIT;
signal y1, y2, y3, y4, y5: BIT;
signal a1, a2, a3, a4, d1, d2, b1, b2, b3, b4, b5, b6, b7, c1, c2, c3, c4 : bit;
begin
block1: n
port map(a => c2, y => d2);
block2: n
port map(a => x1, y => a1);
block3: n
port map(a => x4, y => a4);
block4: no2
port map(a => x2, b => c3, y => d1);
block5: n
port map(a => x3, y => a3);
block6: n
port map(a => x2, y => a2);
block7: o2
port map(a => x1, b => d2, y => b7);
block8: n
port map(a => d2, y => b6);
block9: o2
port map(a => x1, b => d2, y => b5);
block10: na4
port map(a => x3, b => x1, c => a2, d => x4, y => b4);
block11: no2
port map(a => a1, b => x4, y => b3);
block12: na3o2
port map(a => a4, b => d1, c => x3, d => x1, y => b2);
block13: no4
port map(a => a3, b => a4, c => x1, d => a2, y => b1);
y3 <= b1;
block14: noao2
port map(a => a4, b => b7, c => b1, d => b6, y => c4);
y2 <= c4;
block15: no3
port map(a => a3, b => a1, c => x4, y => c3);
y4 <= c3;
block16: nao3
port map(a => b2, b => b3, c => x3, d => a2, y => c2);
y1 <= c2;
block17: na3o2
port map(a => b5, b => b4, c => x4, d => a2, y => c1);
y5 <= c1;
x1 <= '0',
'0' after 50 ns,
'0' after 100 ns,
'0' after 150 ns,
'0' after 200 ns,
'0' after 250 ns,
'0' after 300 ns,
'0' after 350 ns,
'0' after 400 ns,
'1' after 450 ns,
'1' after 500 ns,
'1' after 550 ns,
'1' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
x2 <= '0',
'0' after 50 ns,
'0' after 100 ns,
'0' after 150 ns,
'0' after 200 ns,
'1' after 250 ns,
'1' after 300 ns,
'1' after 350 ns,
'1' after 400 ns,
'0' after 450 ns,
'0' after 500 ns,
'0' after 550 ns,
'0' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
x3 <= '0',
'0' after 50 ns,
'0' after 100 ns,
'1' after 150 ns,
'1' after 200 ns,
'0' after 250 ns,
'0' after 300 ns,
'1' after 350 ns,
'1' after 400 ns,
'0' after 450 ns,
'0' after 500 ns,
'1' after 550 ns,
'1' after 600 ns,
'0' after 650 ns,
'0' after 700 ns,
'1' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
x4 <= '0',
'0' after 50 ns,
'1' after 100 ns,
'0' after 150 ns,
'1' after 200 ns,
'0' after 250 ns,
'1' after 300 ns,
'0' after 350 ns,
'1' after 400 ns,
'0' after 450 ns,
'1' after 500 ns,
'0' after 550 ns,
'1' after 600 ns,
'0' after 650 ns,
'1' after 700 ns,
'0' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
end struct_1;
entity no2 is
port (
a, b : in bit;
y : out bit
);
end no2;
architecture beh_1 of no2 is
begin
y <= not(a or b) after 2 ns;
end beh_1;
entity no3 is
port (
a, b, c : in bit;
y : out bit
);
end no3;
architecture beh_2 of no3 is
begin
y <= not(a or b or c) after 4 ns;
end beh_2;
entity no4 is
port (
a, b, c, d : in bit;
y : out bit
);
end no4;
architecture beh_3 of no4 is
begin
y <= not(a or b or c or d) after 5 ns;
end beh_3;
entity o2 is
port (
a, b : in bit;
y : out bit
);
end o2;
architecture beh_4 of o2 is
begin
y <= a or b;
end beh_4;
entity na3o2 is
port (
a, b, c, d : in bit;
y : out bit
);
end na3o2;
architecture beh_5 of na3o2 is
begin
y <= not(a and b and (c or d)) after 4 ns;
end beh_5;
entity nao3 is
port (
a, b, c, d : in bit;
y : out bit
);
end nao3;
architecture beh_6 of nao3 is
begin
y <= not(a and (b or d or c)) after 5 ns;
end beh_6;
entity noao2 is
port (
a, b, c, d : in bit;
y : out bit
);
end noao2;
architecture beh_7 of noao2 is
begin
y <= not(a or (b and (c or d))) after 4 ns;
end beh_7;
entity n is
port(
a: in bit;
y : out bit
);
end n;
architecture beh_8 of n is
begin
y <= not a after 1 ns;
end beh_8;
entity na4 is
port (
a, b, c, d : in bit;
y : out bit
);
end na4;
architecture beh_9 of na4 is
begin
y <= not(a and b and c and d) after 5 ns;
end beh_9;