entity curcuit1 is
end curcuit1;
architecture struct_1 of curcuit1 is
component my
port (
x1, x2, x3, x4 : in bit;
y1, y2, y3, y4, y5 : out bit
);
end component;
component no2
port (
a, b : in bit;
y : out bit
);
end component;
component no4
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component o2
port (
a, b : in bit;
y : out bit
);
end component;
component no3
port (
a, b, c : in bit;
y : out bit
);
end component;
component nao3
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component noao2
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component na3o2
port (
a, b, c, d : in bit;
y : out bit
);
end component;
component n
port (
a : in bit;
y : out bit
);
end component;
component na4
port (
a, b, c, d : in bit;
y : out bit
);
end component;
signal x1, x2, x3, x4: BIT;
signal y1, y2, y3, y4, y5: BIT;
signal a1, a2, a3, a4, d1, d2, b1, b2, b3, b4, b5, b6, b7, c1, c2, c3, c4 : bit;
begin
block1: n
port map(a => c2, y => d2);
block2: n
port map(a => x1, y => a1);
block3: n
port map(a => x4, y => a4);
block4: no2
port map(a => x2, b => c3, y => d1);
block5: n
port map(a => x3, y => a3);
block6: n
port map(a => x2, y => a2);
block7: o2
port map(a => x1, b => d2, y => b7);
block8: n
port map(a => d2, y => b6);
block9: o2
port map(a => x1, b => d2, y => b5);
block10: na4
port map(a => x3, b => x1, c => a2, d => x4, y => b4);
block11: no2
port map(a => a1, b => x4, y => b3);
block12: na3o2
port map(a => a4, b => d1, c => x3, d => x1, y => b2);
block13: no4
port map(a => a3, b => a4, c => x1, d => a2, y => b1);
y3 <= b1;
block14: noao2
port map(a => a4, b => b7, c => b1, d => b6, y => c4);
y2 <= c4;
block15: no3
port map(a => a3, b => a1, c => x4, y => c3);
y4 <= c3;
block16: nao3
port map(a => b2, b => b3, c => x3, d => a2, y => c2);
y1 <= c2;
block17: na3o2
port map(a => b5, b => b4, c => x4, d => a2, y => c1);
y5 <= c1;
x1 <= '0',
'0' after 50 ns,
'0' after 100 ns,
'0' after 150 ns,
'0' after 200 ns,
'0' after 250 ns,
'0' after 300 ns,
'0' after 350 ns,
'0' after 400 ns,
'1' after 450 ns,
'1' after 500 ns,
'1' after 550 ns,
'1' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
x2 <= '0',
'0' after 50 ns,
'0' after 100 ns,
'0' after 150 ns,
'0' after 200 ns,
'1' after 250 ns,
'1' after 300 ns,
'1' after 350 ns,
'1' after 400 ns,
'0' after 450 ns,
'0' after 500 ns,
'0' after 550 ns,
'0' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
x3 <= '0',
'0' after 50 ns,
'0' after 100 ns,
'1' after 150 ns,
'1' after 200 ns,
'0' after 250 ns,
'0' after 300 ns,
'1' after 350 ns,
'1' after 400 ns,
'0' after 450 ns,
'0' after 500 ns,
'1' after 550 ns,
'1' after 600 ns,
'0' after 650 ns,
'0' after 700 ns,
'1' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
x4 <= '0',
'0' after 50 ns,
'1' after 100 ns,
'0' after 150 ns,
'1' after 200 ns,
'0' after 250 ns,
'1' after 300 ns,
'0' after 350 ns,
'1' after 400 ns,
'0' after 450 ns,
'1' after 500 ns,
'0' after 550 ns,
'1' after 600 ns,
'0' after 650 ns,
'1' after 700 ns,
'0' after 750 ns,
'1' after 800 ns,
'1' after 850 ns;
end struct_1;
entity no2 is
port (
a, b : in bit;
y : out bit
);
end no2;
architecture beh_1 of no2 is
begin
y <= not(a or b) after 2 ns;
end beh_1;
entity no3 is
port (
a, b, c : in bit;
y : out bit
);
end no3;
architecture beh_2 of no3 is
begin
y <= not(a or b or c) after 4 ns;
end beh_2;
entity no4 is
port (
a, b, c, d : in bit;
y : out bit
);
end no4;
architecture beh_3 of no4 is
begin
y <= not(a or b or c or d) after 5 ns;
end beh_3;
entity o2 is
port (
a, b : in bit;
y : out bit
);
end o2;
architecture beh_4 of o2 is
begin
y <= a or b;
end beh_4;
entity na3o2 is
port (
a, b, c, d : in bit;
y : out bit
);
end na3o2;
architecture beh_5 of na3o2 is
begin
y <= not(a and b and (c or d)) after 4 ns;
end beh_5;
entity nao3 is
port (
a, b, c, d : in bit;
y : out bit
);
end nao3;
architecture beh_6 of nao3 is
begin
y <= not(a and (b or d or c)) after 5 ns;
end beh_6;
entity noao2 is
port (
a, b, c, d : in bit;
y : out bit
);
end noao2;
architecture beh_7 of noao2 is
begin
y <= not(a or (b and (c or d))) after 4 ns;
end beh_7;
entity n is
port(
a: in bit;
y : out bit
);
end n;
architecture beh_8 of n is
begin
y <= not a after 1 ns;
end beh_8;
entity na4 is
port (
a, b, c, d : in bit;
y : out bit
);
end na4;
architecture beh_9 of na4 is
begin
y <= not(a and b and c and d) after 5 ns;
end beh_9;