void stm32_dma_transfer BOOL receive FALSE for buff- SPI TRUE for SPI-

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void stm32_dma_transfer(
BOOL receive, /* FALSE for buff->SPI, TRUE for SPI->buff */
const BYTE *buff, /* receive TRUE : 512 byte data block to be transmitted
receive FALSE : Data buffer to store received data */
UINT btr /* receive TRUE : Byte count (must be multiple of 2)
receive FALSE : Byte count (must be 512) */
)
{
DMA_InitTypeDef DMA_InitStructure;
WORD rw_workbyte[] = { 0xffff };
/* shared DMA configuration values */
DMA_InitStructure.DMA_PeripheralBaseAddr = (DWORD)(&(SPI_SD->DR));
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_BufferSize = btr;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_DeInit(DMA_Channel_SPI_SD_RX);
DMA_DeInit(DMA_Channel_SPI_SD_TX);
if ( receive ) {
/* DMA1 channel2 configuration SPI1 RX ---------------------------------------------*/
/* DMA1 channel4 configuration SPI2 RX ---------------------------------------------*/
DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)buff;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_Init(DMA_Channel_SPI_SD_RX, &DMA_InitStructure);
/* DMA1 channel3 configuration SPI1 TX ---------------------------------------------*/
/* DMA1 channel5 configuration SPI2 TX ---------------------------------------------*/
DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)rw_workbyte;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_Init(DMA_Channel_SPI_SD_TX, &DMA_InitStructure);
} else {
#if _FS_READONLY == 0
/* DMA1 channel2 configuration SPI1 RX ---------------------------------------------*/
/* DMA1 channel4 configuration SPI2 RX ---------------------------------------------*/
DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)rw_workbyte;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_Init(DMA_Channel_SPI_SD_RX, &DMA_InitStructure);
/* DMA1 channel3 configuration SPI1 TX ---------------------------------------------*/
/* DMA1 channel5 configuration SPI2 TX ---------------------------------------------*/
DMA_InitStructure.DMA_MemoryBaseAddr = (DWORD)buff;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_Init(DMA_Channel_SPI_SD_TX, &DMA_InitStructure);
#endif
}
/* Enable DMA RX Channel */
DMA_Cmd(DMA_Channel_SPI_SD_RX, ENABLE);
/* Enable DMA TX Channel */
DMA_Cmd(DMA_Channel_SPI_SD_TX, ENABLE);
/* Enable SPI TX/RX request */
SPI_I2S_DMACmd(SPI_SD, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE);
/* Wait until DMA1_Channel 3 Transfer Complete */
/// not needed: while (DMA_GetFlagStatus(DMA_FLAG_SPI_SD_TC_TX) == RESET) { ; }
/* Wait until DMA1_Channel 2 Receive Complete */
while (DMA_GetFlagStatus(DMA_FLAG_SPI_SD_TC_RX) == RESET) { ; }
// same w/o function-call:
// while ( ( ( DMA1->ISR ) & DMA_FLAG_SPI_SD_TC_RX ) == RESET ) { ; }
/* Disable DMA RX Channel */
DMA_Cmd(DMA_Channel_SPI_SD_RX, DISABLE);
/* Disable DMA TX Channel */
DMA_Cmd(DMA_Channel_SPI_SD_TX, DISABLE);
/* Disable SPI RX/TX request */
SPI_I2S_DMACmd(SPI_SD, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE);
}
#endif /* STM32_SD_USE_DMA */