LIBRARY ieee use ieee std_logic_1164 all ENTITY div_cu1 IS PORT reset

LIBRARY ieee;
use ieee.std_logic_1164.all;

ENTITY div_cu1 IS
PORT(reset: IN std_logic;
	start: IN std_logic;
	c_ex: IN std_logic;
	clk: IN std_logic;
	r_mode0: OUT std_logic;
	r_mode1: OUT std_logic;
	alu_enable: OUT std_logic;
	alu_type: OUT std_logic ;
	bit_enable: OUT std_logic;
	b_enable: OUT std_logic;
	q_mode0: OUT std_logic;
	q_mode1: OUT std_logic);
END div_cu1;

ARCHITECTURE state_machine OF div_cu1 IS
SUBTYPE count_integer IS INTEGER RANGE 0 TO 4;
TYPE states IS(idle,init,beg_shift,sub,test1,r_neg,shift,test2,fin_shift);
SIGNAL present_state: states:=idle;
SIGNAL next_state: states:=idle;
SIGNAL present_count: count_integer:=0;
SIGNAL next_count: count_integer:=0;

BEGIN

--------------------Работа счетчиков цикла---------------------
CLKD: PROCESS(clk,reset)
BEGIN
	IF(reset='1')THEN
		present_state<=idle;
		present_count<=0;
	ELSIF(clk'EVENT AND clk='1') THEN
		present_state<=next_state;
		present_count<=next_count;
	END IF;
END PROCESS CLKD;

----------------Процесс перехода из одного состояния-------------
STATE_TRANS: PROCESS(present_state,present_count,start,c_ex)
BEGIN
	next_state <= present_state;
	next_count <= present_count;
CASE present_state IS
	WHEN idle=>
		IF(start='1')THEN
			next_state<=init;
		ELSE
			next_state<=idle;
		END IF;
	next_count<=present_count;
	WHEN init=>
		next_state<=beg_shift;
		next_count<=present_count;
	WHEN beg_shift=>
		next_state<=sub;
		next_count<=present_count;
	WHEN sub=>
		next_state<=test1;
		next_count<=present_count;
	WHEN test1=>
		IF c_ex = '1' THEN
			next_state<=r_neg;
		ELSE next_state<=shift;
		END IF;
		next_count<=present_count;
	WHEN r_neg=>
		next_state<=shift;
		next_count<=present_count;
	WHEN shift=>
		next_state<=test2;
		next_count<=present_count+1;
	WHEN test2=>
		IF present_count < 4 THEN
			next_state <= sub;
		ELSE next_state <= fin_shift;
		END IF;
		next_count<=present_count;
	WHEN fin_shift=>
		next_state <= idle;
		next_count<=present_count;
	WHEN OTHERS=>
		next_state<=idle;
		next_count<=present_count;
	END CASE;
END PROCESS STATE_TRANS;

---Процесс выдачи управляющих сигналов в блок обработки данных DP ---
OUTPUT: PROCESS(present_state)
BEGIN
CASE present_state IS
WHEN idle=>
	r_mode0 <= '0';
	r_mode1 <= '0';
	alu_enable <= '0';
	alu_type <= '0';
	bit_enable <= '0';
	b_enable <= '0';
	q_mode0 <= '0';
	q_mode1 <= '0';
WHEN init=>
	r_mode0 <= '1';
	r_mode1 <= '1';
	alu_enable <= '1';
	alu_type <= '0';
	bit_enable <= '0';
	b_enable <= '1';
	q_mode0 <= '1';
	q_mode1 <= '1';
WHEN beg_shift=>
	r_mode0 <= '1';
	r_mode1 <= '0';
	alu_enable <= '0';
	alu_type <= '0';
	bit_enable <= '1';
	b_enable <= '0';
	q_mode0 <= '1';
	q_mode1 <= '0';
WHEN sub=>
	r_mode0 <= '1';
	r_mode1 <= '1';
	alu_enable <= '1';
	alu_type <= '1';
	bit_enable <= '1';
	b_enable <= '0';
	q_mode0 <= '0';
	q_mode1 <= '0';
WHEN test1=>
	r_mode0 <= '0';
	r_mode1 <= '0';
	alu_enable <= '0';
	alu_type <= '0';
	bit_enable <= '1';
	b_enable <= '0';
	q_mode0 <= '0';
	q_mode1 <= '0';
WHEN r_neg=>
	r_mode0 <= '1';
	r_mode1 <= '1';
	alu_enable <= '1';
	alu_type <= '0';
	bit_enable <= '0';
	b_enable <= '0';
	q_mode0 <= '0';
	q_mode1 <= '0';
WHEN shift=>
	r_mode0 <= '1';
	r_mode1 <= '0';
	alu_enable <= '0';
	bit_enable <= '1';
	b_enable <= '0';
	q_mode0 <= '1';
	q_mode1 <= '0';
WHEN test2=>
	r_mode0 <= '0';
	r_mode1 <= '0';
	alu_enable <= '0';
	bit_enable <= '0';
	b_enable <= '0';
	q_mode0 <= '0';
	q_mode1 <= '0';
WHEN fin_shift=>
	r_mode0 <= '0';
	r_mode1 <= '1';
	alu_enable <= '0';
	bit_enable <= '0';
	b_enable <= '0';
	q_mode0 <= '0';
	q_mode1 <= '0';	
WHEN OTHERS=>
	r_mode0 <= '0';
	r_mode1 <= '0';
	alu_enable <= '0';
	bit_enable <= '0';
	b_enable <= '0';
	q_mode0 <= '0';
	q_mode1 <= '0';
END CASE;
END PROCESS OUTPUT;
END state_machine;