LIBRARY ieee USE ieee NUMERIC_STD ALL USE ieee std_logic_1164 ALL USE

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LIBRARY ieee;
USE ieee.NUMERIC_STD.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Abstarct_Unit IS
PORT(
Clk : IN std_logic;
nRst : IN std_logic;
BU_Addr : IN std_logic_vector (11 DOWNTO 0);
BU_Mem_nReg : IN std_logic;
BU_RD_nWR : IN std_logic;
BU_nStrb : IN std_logic;
q : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
BU_nReady : OUT std_logic;
address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
BU_Dio : INOUT std_logic_vector (15 DOWNTO 0)
);
END Abstarct_Unit ;
--
architecture behavior of abstarct_unit is
--
signal imr : std_logic_vector (15 downto 0) := (others => '0');
signal cgf_reg_1 : std_logic_vector (15 downto 0) := (others => '0');
signal cgf_reg_2 : std_logic_vector (15 downto 0) := (others => '0');
signal start_reset_reg : std_logic_vector (15 downto 0) := (others => '0');
signal cgf_reg_3 : std_logic_vector (15 downto 0) := (others => '0');
signal cgf_reg_4 : std_logic_vector (15 downto 0) := (others => '0');
signal cgf_reg_5 : std_logic_vector (15 downto 0) := (others => '0');
--
signal BU_Do_r : std_logic_vector(15 downto 0);
signal ready_count : std_logic_vector (15 downto 0);
BEGIN
init_MK : process(clk)
begin
if (nRst = '0') then
BU_Do_r <= (others => '0');
BU_nReady <= '1';
address <= (others => '0');
data <= (others => '0');
--
ready_count <= x"0002";
elsif (Clk'event and Clk = '1') then
-- reg
if (BU_Mem_nReg = '0' and BU_nStrb = '1') then
if (BU_RD_nWR = '1') then
case BU_Addr is
when x"000" =>
imr <= BU_Dio;
when x"001" =>
cgf_reg_1 <= BU_Dio;
when x"002" =>
cgf_reg_2 <= BU_Dio;
when x"003" =>
start_reset_reg <= BU_Dio;
when x"007" =>
cgf_reg_3 <= BU_Dio;
when x"008" =>
cgf_reg_4 <= BU_Dio;
when x"009" =>
cgf_reg_5 <= BU_Dio;
when others => null;
end case;
else
case BU_Addr is
when x"000" =>
BU_Do_r <= imr;
when x"001" =>
BU_Do_r <= cgf_reg_1;
when x"002" =>
BU_Do_r <= cgf_reg_2;
when x"003" =>
BU_Do_r <= start_reset_reg;
when x"007" =>
BU_Do_r <= cgf_reg_3;
when x"008" =>
BU_Do_r <= cgf_reg_4;
when x"009" =>
BU_Do_r <= cgf_reg_5;
when others => null;
end case;
end if;
if (ready_count /= x"0")then
BU_nReady <= '1';
ready_count <= ready_count - '1';
end if;
else
if (BU_Mem_nReg = '0' and BU_nStrb = '0') then
if (BU_Mem_nReg = '0' and BU_nStrb = '0' and ready_count = x"1") then
BU_nReady <= '0';
else
BU_nReady <= '1';
ready_count <= x"0001";
end if;
end if;
end if;
-- mem
if (BU_Mem_nReg = '1' and BU_nStrb = '1') then
if (BU_RD_nWR = '1') then
address <= BU_Addr;
data <= BU_Dio;
else
address <= BU_Addr;
BU_Do_r <= q;
end if;
if (ready_count /= x"0")then
BU_nReady <= '1';
ready_count <= ready_count - '1';
end if;
elsif (BU_Mem_nReg = '1' and BU_nStrb = '0' and ready_count = x"1") then
BU_nReady <= '0';
elsif (BU_Mem_nReg = '1') then
BU_nReady <= '1';
ready_count <= x"0001";
end if;
end if;
end process init_MK;
BU_Dio <= BU_Do_r when (BU_RD_nWR = '0') else (others => 'Z');
END ARCHITECTURE behavior;