LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY d_f_f is
	PORT(set, reset, d, clk: IN std_logic;
		 q, nq: OUT std_logic);
END d_f_f;



ARCHITECTURE beh OF d_f_f IS
signal in_q : std_logic;
BEGIN
    q <= in_q;
    nq <= not in_q;
    
	PROCESS(set, reset, clk)
		BEGIN
			IF (reset = '0') THEN
				in_q <= '0';
			ELSIF (set = '0') THEN
				in_q <= '1';
			ELSIF (clk'event AND clk = '1') then
				in_q <= d;
			END IF;
	END PROCESS;
END beh;