azq2 zhumarin dev build cache sources linux-rockchip stable-4 4-rk3288

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azq2@zhumarin:~/dev/build/cache/sources/linux-rockchip/stable-4.4-rk3288-linux$ diff -Naur drivers/clk/rockchip/clk-rk3288.c clk-rk3288.c | colordiff
--- drivers/clk/rockchip/clk-rk3288.c 2019-03-18 21:01:04.830961317 +0200
+++ clk-rk3288.c 2019-03-19 12:58:20.023169588 +0200
@@ -97,14 +97,59 @@
RK3066_PLL_RATE( 312000000, 1, 52, 4),
RK3066_PLL_RATE( 300000000, 1, 50, 4),
RK3066_PLL_RATE( 297000000, 2, 198, 8),
+ RK3066_PLL_RATE_NB( 241500000, 2, 161, 8, 1),//2560*1440@60Hz
RK3066_PLL_RATE( 252000000, 1, 84, 8),
RK3066_PLL_RATE( 216000000, 1, 72, 8),
- RK3066_PLL_RATE( 148500000, 2, 99, 8),
+ RK3066_PLL_RATE( 162000000, 1, 81, 12),//1600x1200@60
+ RK3066_PLL_RATE( 154000000, 1, 77, 12),//1920x1200@60
+ RK3066_PLL_RATE( 148500000, 8, 693, 14),//1920*1080@75
+ RK3066_PLL_RATE( 135000000, 4, 315, 14),//1280*1024@75
RK3066_PLL_RATE( 126000000, 1, 84, 16),
- RK3066_PLL_RATE( 48000000, 1, 64, 32),
+ RK3066_PLL_RATE( 119000000, 3, 238, 16),//1680*1050@60
+ RK3066_PLL_RATE( 108000000, 1, 72, 16),//1280*1024@60
+ RK3066_PLL_RATE( 88750000, 6, 355, 16),//1440*900@60
+ RK3066_PLL_RATE( 71000000, 3, 142, 16),//1280*800@@60
+ RK3066_PLL_RATE( 74250000, 8, 297, 12),//1280*700@60
+ RK3066_PLL_RATE( 32000000, 1, 16, 12),//1024*600@43
+ RK3066_PLL_RATE( 78750000, 4, 210, 16),//1024*768
+ RK3066_PLL_RATE( 78800000, 15, 788, 16),//1280*720@60
+ RK3066_PLL_RATE( 75000000, 2, 100, 16),//1024*768@70
+ RK3066_PLL_RATE( 65000000, 3, 130, 16),//1024*768@@60
+ RK3066_PLL_RATE( 136750000, 8, 547, 12),//1440*900@75
+ RK3066_PLL_RATE( 106500000, 1, 71, 16),//1280*800@75, 1440*900@60
+ RK3066_PLL_RATE( 88750000, 6, 355, 16), //1440x900
+ RK3066_PLL_RATE( 67500000, 8, 315, 14),//640*480@75
+ RK3066_PLL_RATE( 57280000, 25, 716, 12),//832*624
+ RK3066_PLL_RATE( 50000000, 3, 100, 16),//800*600
+ //RK3066_PLL_RATE( 54000000, 4, 162, 18),//640*480@60
+ RK3066_PLL_RATE( 49500000, 1, 33, 16),//800*600@75
+ RK3066_PLL_RATE( 40000000, 3, 80, 16),//800*600@60
+ RK3066_PLL_RATE( 36000000, 1, 24, 16),//800*600
+ RK3066_PLL_RATE( 35500000, 3, 71, 16),//?
+ RK3066_PLL_RATE( 31500000, 3, 73, 16),//640*480@75
+ RK3066_PLL_RATE( 30240000, 25, 504, 16),//650*480
+ RK3066_PLL_RATE( 28320000, 25, 472, 16),//720*400@70
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
+ RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
+};
+
#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
@@ -194,6 +239,7 @@
PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
+PNAME(mux_cifout_p) = { "cif_src", "xin24m" };
PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
@@ -214,7 +260,7 @@
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {
@@ -340,8 +386,6 @@
GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 7, GFLAGS),
- FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
-
COMPOSITE(SCLK_I2S_SRC, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKGATE_CON(4), 1, GFLAGS),
@@ -408,10 +452,12 @@
*/
GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
RK3288_CLKGATE_CON(9), 0, GFLAGS),
-
- FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, 1, 4,
+ /*
+ * We introduce a virtul node of hclk_vodec_pre_v to split one clock
+ * struct with a gate and a fix divider into two node in software.
+ */
+ GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
RK3288_CLKGATE_CON(3), 10, GFLAGS),
-
GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
RK3288_CLKGATE_CON(9), 1, GFLAGS),
@@ -429,7 +475,7 @@
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
@@ -917,6 +963,18 @@
return;
}
+ /* xin12m is created by an cru-internal divider */
+ clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
+ if (IS_ERR(clk))
+ pr_warn("%s: could not register clock xin12m: %ld\n",
+ __func__, PTR_ERR(clk));
+
+ clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
+ "hclk_vcodec_pre_v", 0, 1, 4);
+ if (IS_ERR(clk))
+ pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
+ __func__, PTR_ERR(clk));
+
/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
if (IS_ERR(clk))